1. Field of the Invention
The invention relates to a DRAM memory circuit with sense amplifiers. As is known, the acronym DRAM stands for digital random access memory having a multiplicity of memory cells which are directly selectively addressable in order optionally to write in or read out binary memory data at said memory cells.
2. Description of the Related Art
DRAMs usually contain one or more cell arrays, each of which contains a multiplicity of memory cells forming a matrix-type arrangement of rows and columns. Each column is assigned a column line, which comprises two cores and is referred to as a “bit line”. Each row is assigned a row select line, which is referred to as a “word line”. A cell is accessed by activation of a word line in a manner dependent on a row address, as a result of which a transistor is turned on in each memory cell of the relevant row. This transistor connects the memory element of the cell to a core of the respectively assigned bit line, so that a differential voltage can be sensed between the two bit line cores, with the polarity of the differential voltage depending on the binary value of the datum stored in the relevant cell.
The differential voltage, which generally has only a relatively small magnitude, is applied for evaluation purposes to a differential amplifier which is individually assigned to the relevant bit line and is generally referred to as “sense amplifier”. The function of the sense amplifier is to pull the sensed differential voltage apart in such a way that the lower potential is pulled down to a defined low logic potential and the higher potential is pulled up to a defined high logic potential. The sense amplifier contains two line rails, which can be connected to the two bit line cores, and two transistor circuits, each of which contains, for its part, two switching transistors individually assigned to the two rails. The first transistor circuit can be activated by a first switching signal in order to pull the rail of the lower potential of the sensed differential voltage down to the low logic potential via the switching transistor assigned to it. The second transistor circuit can be activated by a second switching signal in order to pull the rail of the higher potential of the sensed differential voltage up to the high logic potential via the switching transistor assigned to it.
The differential voltage amplified in this way is coupled to the memory element of the memory cell via the assigned bit line cores in order to refresh the previously stored datum. In order to forward the sensed datum to the data port of the memory circuit, a column select signal dependent on a column address is generated to close a data line switch which connects the rails of the sense amplifier of the addressed column to a two-core data line.
DRAM memory circuits are usually produced as integrated circuits on semiconductor chips, it being recommended for various known reasons to use field-effect transistors (FETs) as far as possible. This also applies to the sense amplifiers. In the sense amplifiers for those switching transistors which pull the lower potential of the sensed differential voltage down further, use has been made heretofore of field-effect transistors of that conduction type in the case of which the channel is at low impedance if the gate potential is higher than the source potential at least by the amount of the field-effect transistor threshold voltage Vth. For the switching transistors which pull the higher potential of the sensed differential voltage further up, use has been made of field-effect transistors of the opposite conduction type, in the case of which the channel is at low impedance if the gate potential is lower than the source potential at least by the amount of the field-effect transistor threshold voltage Vth. In other words, where “higher” potential means “more positive”, use has been made of N-channel field-effect transistors (N-FETs) for the pull-down switching transistors and P-channel field-effect transistors (P-FETs) for the pull-up switching transistors.
In order to form field-effect transistors of different conduction types on the chip of an integrated circuit, “well” regions doped with impurity for the respectively opposite conduction type have to be created in the substrate. Each well requires, on its surface, space for the formation of the source, drain and channel zones of the field-effect transistors and for the formation of the contact for applying the required well potential. This useful space has to have a certain safety clearance with respect to the edge where the adjacent well of the other conduction type adjoins, because said edge cannot be defined with arbitrary precision with regard to the accuracy of its position and also with regard to its distinctness.
This is because during the production of the wells edge effects arise, e.g., as a result of the scattering of the doping implanting beam at photoresist edges. The doping profile at the boundary between a P-type well that is to be formed for the N-FETs and an N-type well that is to be formed for the P-FETs thus becomes ever more difficult to control with increasing miniaturization of the feature sizes. A well may, e.g., taper toward the edge or extend upward or downward. Such edge effects become apparent in an alteration of the threshold voltage of all the transistors near the edge. In a sense amplifier, a one-sided alteration of the threshold voltage may lead to an extremely undesirable asymmetry of the amplifier behavior.
The aforementioned edge effects thus make it necessary to provide a safety zone between the utilized surface of a P-type well and the utilized surface of an N-type well. This safety zone is in principle an unused space and thus undesirably increases the area requirement of the integrated circuit. The smaller the safety zones are made in order to reduce the area requirement, the greater the risk of the aforementioned asymmetry and, consequently, rejects in chip production.